Journal of Global Research in Computer Sciences
MenuISSN: 2229-371X
ISSN: 2229-371X
| Chetan Sharma (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida, UP, India) |
| Corresponding Author:Chetan Sharma,E-mail:[email protected] |
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This paper gives a new type of switch design using veriology. Switch is an important part of VLSI chips. To making any RTL (Register Transfer Level) switch is required for transmitting the data through different ports. In this switch, control over transfer of data is also provided by using different set of registers as described in this paper. Another importance of this switch is the expandable properties by using reserve space for future use.
Keywords |
| Icarus tool, GTK wave, Gvim editor, RTL, Comparator cum receiver, Test bench |
INTRODUCTION |
| Register Transfer Level (RTL) performs the sequence of register transfer in one clock or more than one clock cycle. It has two parts Data subsystem and Control subsystem. For any data transmission two things requires firstly set of registers secondly control of sequencing of that registers as shown in fig (a). |
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| For design any VLSI chip firstly RTL of that chip’s specification is designed then test bench is written using HDL (Hardware descriptive language) either VHDL or Verilog for testing the functionality of the chip. After this frontend part the whole code is given to Backend team for fabrication process. |
| Four port switch is an important component of any design for transmitting data through selecting a particular port depending on the bits of incoming data. It gives all the signals such as Ready, Read, Detain, Dataout for reliable transmission of data. All the designing is done here by Icarus tool using verilog with GVIM editor. Wave form is gotten by the tool GTK wave. |
REGISTER SETS |
| There are four register sets in the architecture of this switch: |
| DA:It is 8 bit register which use to store the destination address of data. Last two bits of DA decides that which port will be use for transmission of 8 bit data as shown in fig (c) and all other 6 bit is reserve for future use. These blank spaces can be programmed according to user requirement. |
| SA:It is 8 bit register which is used to store the source address of Input data. |
| LENGTH:It is 8 bit register which is used to decide that how many number of byte will have to be transmitted. After completing the number of byte read from Length register, transmission is stopped. |
| CONTROL:It is also 8 bit register which is used to control the flow of transmission. If 0th bit is 0 then no operation will be performed else transmission will happen. |
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SIGNALS DESCRIPTION |
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WORKING |
| When the 8 bit data comes to switch by Datain signal then this byte is stored in DA register which decides the port by which it has to be out. Second byte comes to SA register which tell the source address of the input data. Third byte of input goes to LENGTH register which decides the number of byte to be out via port. Fourth byte comes to CONTROL register which decides whether the data should transfer or not. Now if read signal of corresponding port is 1 then ready signal of same port become high. Then next coming bytes will transfer to output 0 or output 1 or output 2 or output 3 depending on first four bytes. On completing the transmission data transfer signal become high. |
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DESIGNING STEPS |
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CONCLUSION |
| In this paper the data transfer through controlled switch is designed using Verilog. It has minimum delay and high controllability on transmission of data from source address to destination address because of using Length and Control register. This design also provides the less silicon area consumption due to the reason of simple architecture. |
References |
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