基于故障免费选通控制数控延时线

文摘

组合电路设计是故障免费NAND-based数控延迟线中(DCDL)提供一个故障问题,可能会限制他们的使用在许多应用程序中。故障自由控制基于数控延迟线路克服这个限制,开放使用的故障免费NAND-based DCDLs在范围广泛的应用程序。提出的基于故障自由控制数控延迟线路维护相同的分辨率和最小延迟先前提出的故障免费NAND-based DCDL。这种分析后,三个驱动电路延迟控制位也提出了。提出DCDLs设计在90 nm CMOS技术。仿真结果表明,新的电路导致最低的决议,有点恶化的最小延迟对前面提出的DCDL最低的延迟。模拟也确认开发了故障模型和分级策略的正确性。示例应用程序,提出了DCDL是用来识别一个Alldigital扩展频谱时钟发生器(SSCG)。的使用提出DCDL绝对在这个电路可以减少峰使用三态输出抖动对SSCG DCDLs逆变器。

索引词

全数字迟延锁定环(ADDLL) alldigital锁相环(ADPLL)延迟线,数控振荡器(DCO),拖鞋,放大器,扩展频谱时钟发生器(SSCG)。

介绍

在最近deep-submicrometer CMOS工艺,timedomain数字信号的分辨率是变得比电压模拟信号的分辨率更高的[1]。这种说法如今将走向一个新的电路设计范例,传统的模拟信号处理将逐步取代在数字域处理的倍。在这个小说模式,数控延迟线(DCDL)应该扮演digital-toanalogconverters在传统的角色,analog-intensive,电路。从更实际的角度来看,如今,DCDLs关键块在许多应用程序中,像全数字锁相环(ADPLL)[2] -[8],全数字DLL (ADDLL) [9] - [11], alldigital扩展频谱时钟生成器(SSCGs),[18]和超宽波段接收机(UWB)等功能。线性反馈移位寄存器是用于生成测试向量。它使用反馈和修改本身在每一个时钟的上升。DCDL(数控延迟线路)是使用delay-cells链和MUX细胞选择所需的输出。在这些mux-based DCDLs MUX延迟增加,细胞的数量的增加。的大时间MUXbased DCDLs可以减少通过使用一个基于树的多路复用器拓扑导致不规则结构复杂的布局设计,因此,也增加DCDL的非线性。不同于上面的方法,在这个DCDL拓扑构造每个细胞通过使用逻辑门。这显然解决相关的权衡MUX之前的结构。深化分析显示的输入电容DCDL线性增长细胞的数量。 This clearly reintroduces a trade-off between the number of cells. In [2]–[5], the DCDL is constructed by using a regular cascade of equal delay elements (DE). In this circuit, the multiplexer of previous DCDL is theoretically spread among all cells. In this way the minimum delay is very low and becomes independent of the number of cells. In addition the highly regular topology allows a simple layout organization [8] which provides very low nonlinearity layout effects. Each DE in [2]–[5] is constructed by using only NAND gates, obtaining a very good linearity and resolution. The DCDL proposed in [8] uses again a structure of cascaded delay elements. Differently from [8]–[11], each element is constructed by using three-state inverters (TINV). Since the pull-up network of a TINV requires two series devices whereas a NAND gate uses a single device in the pull-up, we can expect that the resolution of this solution is higher than the resolution of NAND-based DCDLs.

[1]中提出的DCDL也是基于一连串的平等延迟元素,它允许一个简单的组织布局。在这种情况下每个延迟元素是由使用一个逆变器和一个反相多路复用器。逆变器和mux拓扑结构有两个缺点。第一个缺点是由于逆变器和多路复用器的不同延迟导致奇数和偶数控制代码之间的不匹配。第二个缺点是由于大型多路复用器的延迟,它提供了一种分辨率高于分辨率的NAND DCDLs和TINV-based DCDLs。故障在系统使用DCDLs是一种常见的设计问题。在最常见的应用程序中,DCDLs受聘处理时钟信号,因此需要一个完美的操作。避免故障的一个必要条件是设计一个DCDL中有任何错误的延迟控制代码转换。这是一个问题在DCDLdesign级别。众所周知,很多方法避免故障mux-based DCDLs。 It is interesting to observe that the DCDL topologies of [8], from a logical point of view, correspond to distributed MUX-based structure. Glitching in these topologies can be avoided by using a thermometer code for the control-bits, or using the approach of [3]. On the other hand the NAND-based DCDL topology of [2]–[5] presents a glitching problem that, to the best of our knowledge, is still not known in Literature. It is worth to note that in the ADDLL topologies of the DCDL glitching is filtered by the phase detector and harmonic locking circuitry during locking phase. In other applications, however, the presence of this glitching phenomenon can substantially limit the employ of NANDbased DCDLs. This represents a substantial drawback of this topology in comparison to the solutions of [8] and [11].The errors that in some applications can originate from DCDL glitching will be also discussed within this paper.This paper gives two contributions to the design of NAND-based DCDLs. First it is shown and analyzed the glitching problem of the NAND-based DCDL .The proposed NAND-based DCDL allows to achieve a resolution, similarly to the NAND-based DCDL. The paper is organized as follows. In the same DCDLs in comparison to previously proposed structures. Finally, Section VI describes the employ of proposed DCDL to implement an All-digital SSCG designed with section the glitching problem of this DCDL is analyzed. The structure of proposed, glitch-free, NAND-based DCDL is presented in Section III. Section IV analyzes theoretically the novel DCDL structure by deriving the conditions (timing constraints) needed to avoid glitching in proposed circuit. These results are used to propose three different driving circuits for the delay control-bits of proposed DCDL.

之前提出NAND-BASED DCDL和故障

图1 (b)表明,结构表现出更严重的故障问题,延迟控制代码是增长超过1。图的分析,在这种情况下,显示,在最坏的情况下,四个路径传播DCDL内部结构和可能创建一个multiple-glitch延迟线的输出。控制代码增加时,输出的逻辑状态变得依赖的一部分的DCDL和开关从1到逻辑状态依赖。这个开关可以确定输出故障。这也表明,没有可能发生故障时控制代码却降低了。控制代码时增加了一个故障问题可以避免的延迟信号对信号(见图1 (a)。然而,这个解决方案并不能解决故障问题增加了多个控制代码时(见图1 (b))。图2显示了一个基于晶体管级仿真的NAND DCDL由64个元素。的控制代码DCDL首先从9到62,后来,从62调整为9。DCDL输出报告在第三图的曲线(”(基于NAND [2] - [5])”)。码字增加时,可以观察到三个故障的存在DCDL输出。 As observed before, when the code word is decreased, no output glitching occurs. The glitching problem in still more severe when the DCDL is closed in a ring-oscillator topology to build a DCO. Fig. shows the simulation of a ring-oscillator based DCO designed by using the NAND-based DCDL. It can be observed that the delay control-code is initially equal to 20, this corresponds to an oscillation frequency of about 500 MHz. When delay control-code is switched from 20 to 30 a glitch is produced by the DCDL. Because of the feedback topology of the DCO, this glitch remains entrapped in the ring-oscillator, providing a strong modification also of the steady-state response of the circuit. Substantially the ring-oscillator enter in an oscillation state with more than one output rising-edge for oscillation period. The output frequency of the DCO, in these conditions, should be of about 333 MHz, while the circuit provides an output with a frequency which varies between 800 MHz and 1.2 GHz, with a mean value which corresponds to three times the desired frequency GHz .Afterwards the delay-control code is switched back to 20. Note that this switching does not result in DCDL glitching, however the ring-oscillator state remains compromised by the presence of the glitch in previous control-code switching. The DCO output frequency, in fact, should return to 500 MHz, while the output frequency of the circuit varies between 1.3 and 2.0 GHz with a mean value of 1.5 GHz.

提出了闪光灯DCDL为基础的控制

提出的结构DCDL图3所示。在这个数字“一”表示每一个与非门的快速输入。盖茨标有“D”,代表负载均衡虚拟细胞补充道。

根据所选择的控制位编码,每个delayelement (DE)可以在三种可能的州之一。在这种状态下与非“3”的输出等于1和NAND“4”允许较低的NAND盖茨的信号传播链。在这种状态下上DE传递到输出的输入与非“3”。下一个德(i = c + 1)在post-turn-state (Si = 1, Ti = 0)。在这个DE NAND“4”的输出是stuckat 1,通过允许传播,在前面的DE turn-state(这是),输出的NAND“3”与非“4”。所有剩余的DEs(因为我> c + 1)再次在turn-state (Si = Ti = 1)。的完美转换属性提出DCDL概念上简单的演示。K + 1日德切换后,所有细胞都在pass-state或turn-state。在这些条件下可以自由改变状态的DEs pass-state turn-state,因为这种变化不会影响信号的逻辑状态。这个过程有缺陷需要三步DCDL的切换。 The following section provides a more detailed analysis of the glitching of proposed circuit in order to show that a glitchfree operation can also be achieved by using a properly designed two-step switching mechanism. The last signal plotted in Fig. 2 is the output of proposed DCDL of Fig. 4, simulated by using the above described three step switching mechanism, and in the same conditions of the NAND-based DCDL [12]–[15].This simulation confirms that no glitching is obtained at the output of proposed DCDL. In Fig. 3, by increasing the control code by one, two NAND gates are inserted in the signal propagation path between In and Out. The circuit of Fig. 3 is an inverting DCDL. In this circuit it is interesting to observe that the first DE is never in post-turn state,therefore T0 is always 1. This observation allows to construct a non-inverting DCDL by modifying only the first DE, as shown in Fig. 4. In this circuit the NAND gates “1” and “2” of the first DE have been deleted, together with signal T0.The signal of the second DE is now equal to In, therefore the whole behavior of the DCDL is non-inverting. The last signal plotted in Fig. 3 is the output of DCO designed by using proposed DCDL of Fig. 4. This simulation confirms that no glitching is obtained at the output and this results in a correct DCO operation. In fact the simulation shows that the DCO output switches correctly from 500 to 333 MHz and back to 500 MHz, without any glitch or any problem.

提出DCDL完美切换和控制位驱动电路

在前一节中我们已经看到的完美运行提出DCDL可以获得与threestep切换机制:从延迟开关控制代码c = c = h k延迟控制代码,首先,k + 1日德从post-turn-state转向turn-state;下所有德从通过转向turn-state(反之亦然),最后转向post-turn-state h + 1日德。这种开关机制提出的缺点是缓慢而可能导致的不是简单的驱动电路DCDL控制位。

图5所示。可能的驱动电路的控制位提出DCDL: (a)如果信号延迟与不同的LH / HL延迟使用NAND-based电路;(b)使用时钟信号延迟延迟(c)如果延迟与不同的LH / HL延迟通过使用时钟延迟和double-clock人字拖图5显示了三种可能的驱动电路,可用于生成DCDL提出的控制位。图6可以通过分析指出,如果信号必须被推迟对Ti信号,它可能是有用的不同延迟LH和HL转换。同样值得注意的是,为了避免故障DCDL, Si和Ti信号本身必须是故障免费。按照这种推理,提出了驱动电路,它假定Ti信号作为输出生成的人字拖,,同时,适当时间DCDL考虑systemlevel方面,和作为deglitching元素。图5(一个)显示第一个驾驶技术。在这个解决方案中每个信号都是通过使用一个触发器,后跟一个NAND-based电路提出了不同的LH和HL传播延迟。这个解决方案的缺点是相对较大的复杂性,因为,对于每一个信号,驱动电路由三个逻辑门是必要的(除了触发器)。图5 (b)驱动电路的结果比电路的简单图5(一个)。 In this second solution signals are delayed by delaying the clock signal of the flip-flops. The clock signal delay can be easily obtained by properly designing the clocktree. In a standard-cells design flow based on automatic place and route, a different clock-tree delay can be obtained on a flip-flop by flip-flop bases by using the useful-skew feature of the tools. The third solution of Fig. 5(c) joins the advantages of the two previous solutions. The circuit of Fig. 5(c) is based on the employ of a special flip-flop that we will name doubleclock flip-flop in the following. This flip-flop employs two different clock signals: one clock signal is used to capture the high logic-state of the D input while another clock signal captures the low logic-state of the D input. In the driving circuit of Fig. 5(c), this special flip-flop allows to control separately the LH and HL instants of switch of the signals through the delays of the two clock signals.

分级和仿真结果

为了验证解决方案的有效性,无花果的电路。1 - 5的DCDL [8] 90 - nmcmos技术设计,1.0 v电源电压和使用标准的设备。所有DCDLs,考虑长度是64个元素。评估DCDLs的表演之前,一系列的模拟来验证故障行为被执行。目的模拟试验台被认为是延迟控制代码的改变通过使用000随机延迟控制代码的测试向量。在这种情况下,电路的图5208表现出故障。验证了提出的glitchingbehavior DCDL考虑图4的波形,并通过改变两个延迟。图5显示了获得仿真结果和比较这些结果与两个时间限制。两个轴上的图提出了延迟,规范化与非门的传播延迟。一个圆和一个十字架是用来表示任何故障或模拟glitchingbehavior观察,分别。

的分析,证实了模型的正确性在第四节,强调有效的两个约束条件(5),(6)代表一个最坏的情况。提出了非反相的最小延迟DCDL非常接近的最小延迟NAND-based DCDL [12] - [15]。最低的是通过TINV-based DCDL [8]。这个解决方案,然而,支付高出58%对NANDbased DCDL和更高的功耗。请注意,提出DCDLs导致较低的功耗对TINV-based DCDL[8]自从晶体管上浆中可以更有效提出电路对TINV-based DCDL, PMOS上浆的nMOS的约2.5倍。图6显示了模拟INL的提议相DCDL端。

结论

一个NAND-based DCDL,避免了以前的电路的故障问题已经提出。小说的时间模型DCDL结构了展示的完美属性提出了电路。作为额外的结果,开发模式提供了时间限制还需要对DCDL控制位为保证完美操作。三个不同的驱动电路DCDL控制位,验证给定的时间限制,本文提出了。仿真结果证实了模型的正确性,表明提出的解决方案提高分辨率对先前的方法。示例应用程序提出DCDL用来实现全数字SSCG。DCDL提出的采用这种电路可以减少峰绝对超过55%的输出抖动对一个使用三态SSCG inverter-based DCDLs。

引用

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