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高速I/O中使用锁相环的时钟策略

摘要

由于信号完整性问题，正常的时钟策略不适用于非常高的频率。任何高速电路的速度最终都是由与之相关的I/O电路决定的。本文描述了不同时钟策略之间的比较，并给出了这些策略的应用范围。在1970年到1990年期间，门的切换非常缓慢，以至于数字信号实际上看起来像1和0。信号传播的模拟建模是不必要的。在今天的速度下，系统中简单的无源元素，即电线、PC板走线、连接器和芯片包，构成了整体信号延迟的重要部分。此外，这些元素会导致故障、重置、逻辑错误和其他问题。随着设计被推向更高的运行速度。对于高性能板，mcm和系统，互连设计必须指定并从电气要求驱动:(1)满足设置和保持时间并保证信号完整性(2)避免设计/布局/验证迭代(3)确保低制造成本和高可靠性。传统的信令技术，称为公共时钟(CC)信令[通过引用支持]，依赖于分配给所有总线代理的单一系统时钟作为公共参考。所有事务都使用这个公共时钟引用以锁到锁的方式执行。 Trace propagation delays are governed by trace length. Trace lengths are often governed by the thermal solution. As speeds increase, heat sinks get larger and force components farther away from each other, which limit the speed of a common-clock bus design. Source-Synchronous clocking refers to the technique of sourcing a clock along with the data. Specifically, the timing of unidirectional data signals is referenced to a clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master). A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT A more radical approach for reducing the clocking overhead is to eliminate the clock entirely. Such designs are called self-timed designs. Self-timed systems provide completion information along with their data values. This completion information controls the sequencing of data through the machine and can be encoded in the data (true self-timing) or can be generated by using delay-matching circuits.

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