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基于MIPS的32位RISC CPU设计

摘要

本课题的主要目标是基于MIPS的32位RISC CPU的仿真与合成。本课题涉及设计一个简单的RISC处理器并进行仿真。精简指令集编译器(RISC)是一种被设计用来执行少量指令集的微处理器，目的是提高处理器的整体速度。本文以精简指令集计算机(RISC) CPU指令集为基础，分析了MIPS指令格式、指令数据路径、解码器模块功能和设计理论。在此基础上，采用流水线设计的方法对基于RISC CPU指令集的32位CPU的指令提取(IF)、指令解码器(ID)、执行(EXE)、数据存储(MEM)、回写(WB)模块进行了仿真。IF模块的功能是从内存中获取指令。ID级的功能是发送控制命令，即向控制单元发送指令并在此进行解码。EXE阶段执行算术。EXE阶段的主要组件是ALU。MEM阶段从内存中读取数据并将数据存储到内存中，如果指令不是内存/IO指令，则将结果发送到WB阶段。最后WB阶段负责结果的写入、数据的存储和数据的输入注册。 The purpose of WB stage is to write data to destination register.The idea of this project was to create a RISC processor as a building block in VHDL than later easily can be included in a larger design. It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic. However at a high level of complexity it is easier to implement the function in software. In this project for simulation we use Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. The language we used here is VHDL, and tools required here are MODELSIM III SE 6.4b – Simulation XILINX-ISE 10.1 – Synthesis. The applications are automatic robot control, bottling plant.

N.Alekya, P。Ganesh库马尔

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