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数字锁相环在直流电机转速保持中的Fpga实现

摘要

数字锁相环能够克服其他控制器如模糊逻辑控制器、模拟锁相环和PID控制器的缺点和性能问题。因此，采用数字锁相环(DPLL)控制器实现直流电机的转速控制是目前研究的热点。重点介绍了FPGA(现场可编程门阵列)数字锁相环和PWM发生器的实现。数字锁相环提供了一个高度稳定的频率控制比其他控制器，如模拟锁相环，PID和模糊逻辑控制器。闭环传感元件为光学编码器，输出频率与电机转速成正比的脉冲序列。该脉冲序列将由数字锁相环同步到FPGA内部由石英晶体振荡器产生的给定精确频率的参考脉冲序列。两个脉冲串之间的相位差由相位检波器通过计算两个脉冲的脉宽来测量。相位检波器将相位差转换为可由环路滤波器进行数字处理的数值。回路滤波器起着调节器的作用。该锁相环的DCO(数字控制振荡器)模块被一组电机和编码器的组合所取代。 The DC motor terminal voltages controlled using MOSFET based chopper circuit. The chopper is driven by a précised frequency PWM signal. The result of the project shows that motor speed is not affected so much with the varying loads. On loading the motor speed slow down for about 40 rpm (10%) of its normal speed 400rpm, on unloading the motor speed is hunting to its normal speed 400 rpm. The motor used in this experiment is a DC motor with rated speed of 500 rpm and rated voltage of 12 Volt and rated current of 1 Ampere. Results show the behavior of the designed digital PLL and PWM generator circuits in FPGA.

巴斯卡尔P.C.1和古普塔d.k

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