算术和内存地址计算使用加法器操作执行。因此,设计方案形成一个重要的电子芯片设计的一个功能子集。BCD数字在数字系统中发挥重要的作用。各自对BCD执行算术运算数字电路设计。执行BCD, BCD蛇。BCD的加法器,但缺点是低速运行由于延迟传播进行输出。这种低速操作会影响整个系统的操作使用。随着技术是推进日复一日对芯片高速的需求。为了克服这个缺点,使用本文提出了CLA BCD加法器。提出设计是试图减少延迟,从而提高响应速度。 In existing BCD architecture, RCA is used to add numbers. The delay of RCA is high so it is effecting the speed of adder. So in the proposed design, CLA is used instead of RCA and also a parallel prefix network is to be used to produce the carry outputs for all stages. In this paper, a BCD adder using CLA is to be designed for 8, 16, 32, 64 and 128-bit size using VHDL with the help of ISE Xilinx design suite 14.1. The designed adder will be functionally verified by using ISIM simulator. Later, it will be synthesized using XST synthesizer to get the area (in terms of LUTS) and delay(ns). Finally, the designed BCD adders will be compared with conventional BCD adder in terms of delay(ns).
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